Time multiplexed processor bus

ABSTRACT

A multi-master processor bus and a method of processing data which permits multiple microprocessors to communicate freely and inexpensively among themselves and various system resources. The bus uses a multiphase clock and latches to provide time slice signals to sequentially activate each processor, one at a time in a repetitive sequence. The bus includes cables and terminals for each of the cables with means for interconnecting each of the modules in series daisy chain fashion to selected cables.

The present invention relates to a multi-master processor bus whichpermits multiple microprocessors to communicate freely and inexpensivelyamong themselves and various system resources. The invention permitseasy expansion of functionality without modification of the individualprocessors and thus contemplates a very large scale computer systemwhich can be built with a number of microprocessors.

THE PRIOR ART

The current state of the art technology allows only one to threeprocessors to share a common system bus at the same time. Many of thebus structures in use today cannot even handle two processors withoutelaborate and expensive direct memory access (DMA) controllers, busmultiplexers and conflict resolvers.

Current microprocessor system buses are extremely wasteful in exploitingbus bandwidth. When a microprocessor accesses a typical system bus, itwill wait on the bus until it receives or transmits the desired data.Most microprocessors have a bus cycle time of 500 to 1000 nsec. Theactual data transfer could be accomplished within a fraction of thatperiod. While a given processor is waiting for its data, it effectivelylocks out any other processors from using the bus.

THE ADVANCE OF THE PRESENT INVENTION

The multi-master processor bus of the present invention allows a largenumber (N) of processors to share a common system bus simultaneouslywithout conflict and requires very little or no hardware overhead andvery simple software that is embedded within each processor board. Eachprocessor board is identical to each other in every respect,mechanically, electrically, and in firmware (if desired). A limit ofeight master processors is typically chosen as a practical guide forassembly and test, but additional processors theoretically could beadded to the system.

In accordance with the present invention the backplane that supports thebus is a simple standard network of wires that interconnects the varioussystem modules. The system controller is made up of only two standardmedium scale integration chips (MSIs) that can be integrated within thebackplane.

The multi-master processor bus greatly increases the effective bandwidthof the system bus by employing a time multiplex packet drivenarchitecture. The architecture allows unlimited global system resources,it allows each master processor unlimited private resources and allowsmultiple multi-master processor buses to be interconnected.

THE PRESENT INVENTION

More specifically, the present invention relates to a multi-masterprocessor bus for interconnecting a plurality of processor modulescomprising a plurality of cables each having a plurality of connectinglines to a plurality of sets of processor module terminals forattachment to a plurality of processor modules. Cables are supplying atleast the following purposes: interrupt request; interrupt acknowledge;address and control; time slice vector and clock; and data. Clock meansprovides periodic impulses and counter means is assocated with the clockto count the impulses and generate a multiphase clock. The cableconnections include cables and means for interconnecting each of themodules in series daisy chain fashion to both the interrupt request andinterrupt acknowledge cables.

The invention also contemplates a method of processing data using aplurality of master processors which are provided with parallel cableconnections to a bus. By the method one of the master processor isselected arbitrarily to be the master master processor to designatewhich processor shall be active, accept data or output data to otherprocessors. Time slice signals are then provided to sequentially grantaccess to the bus by each of the processors one at a time in arepetitive sequence.

DRAWINGS OF A PREFERRED EMBODIMENT OF THE INVENTION

A preferred embodiment of the present invention is illustrated in theaccompanying drawings in which:

FIG. 1 is an overall block schematic diagram of the multi-masterprocessor bus in the connection system, showing interconnections of aplurality of processors;

FIG. 2 is a more detailed schematic block diagram showing abus/processor interface typical of the present invention;

FIG. 2A is a block diagram showing the interrupt request enable/disableportion of a processor module;

FIG. 3 is a similar block diagram of a bus/resource module interfaceexample;

FIG. 4 is another block diagram showing a further bus/resource interfaceexample, a module's interrupt request logic;

FIG. 5 is a multi-master processor bus backplane schematic with certainblock input elements illustrated;

FIGS. 6, 7, and 8 are each composite time scale graphs relating tovarious signals within a multi-master system.

The system in accordance with the present invention consists of masterprocessor modules, global resource modules, system timing controller anda backplane.

A master processor module contains a processor and some combination ofread only memory, read/write memory, input/output devices and controllogic. These components are for the private use of the processor. Theprocessor module also contains an interface to the system bus. Onlyprocessor modules may access the system bus. Processor modules are alsoknown as bus masters or master modules.

A global resource module may be any combination of read only memory(ROM), read/write random access memory (RAM), input and output devices(I/O), and dedicated processor subsystems. It also contains an interfaceto the system bus. Global resource modules may not access the system busunless specifically requested by a master processor.

The system timing controller consists of a master clock and logic toprovide an N phase system clock that is encoded into log 2N bit fields.This logic preferably is incorporated into the backplane bus circuitboard.

The backplane is a simple linear array of sockets and interconnectionsfor the system. The various system modules may be plugged into thebackplane in any sequence and in any quantity as long as the masterprocessor limit of N is not exceeded.

Another feature of the multi-master processor bus system is that eachsystem module may run asynchronously with respect to each other Thesystem bus, however, is a synchronous bus. The multi-master processorbus is also called a "global bus".

Each master processor module may be a self-sufficient computer, capableof operating even if it is not plugged into the multi-master processorbus.

Referring first to FIG. 1, a multi-master processor bus system is shownschematically. In this diagram, there are a plurality of processormodules 10a, 10b, 10c, and implicitly there are other modules up to 10m. Similarly, there are shown resource modules 12a and 12n with thepossibility of intermediate resource modules. The resource modules asexplained above are connected to the multi-master processing bus, orglobal bus 40 only in response to actions or commands from a processormodule 10a, 10b, 10c . . . .

The multi-master processor bus 40 consists of a plurality of multi-wirecables. One of those cables is time slice vector and clock bus 14.Connections are made to the bus 14 from the various modules byconnection lines. Processor module 10a is connected by connection 14a.Resource module 12a is connected to bus 14 by lines 14b. Processormodule 10b is connected by lines 14c. Processor module 10c is connectedby lines 14d. Processor resource module 12n is connected by lines 14n.As illustrated in FIG. 1, the processor modules and the resource modulesare connected in parallel with one another to the bus 40. The time slicevector and clock bus 14 is provided an input from a counter 16 which istriggered by a 16 megahertz clock 18. The output of the counter 16 isapplied to buffer 20 which also buffers the clock 18. The buffer puts acount signal comprised of a number of binary pulses, the number ofpulses being related to the number of master processor modules beingutilized in the system out on the time slice vector and clock bus 14 andthereby enables application of the count signal to each of the modules.The count signal is decoded by circuitry in each master processor modulein a manner which will hereinafter be described.

The multi-master processor bus also includes an interrupt acknowledgebus 22 and an interrupt request bus 24. An interrupt request signal canbe generated by any of the modules and placed on the interrupt requestbus 24 by connection buses 24a, 24b, 24c, 24d, and 24in. The interruptrequest signal is applied by the interrupt request bus 24 to the inputof the first processor module 10a via bus 24x. The interrupt requestsignal is then daisy chained down the line of master processor andresource modules in the usual well-known manner as shown. Although theinterrupt request signal is usually generated by a resource module itcould be generated by a master processor module.

An interrupt acknowledge signal can be generated by any of the masterprocessor modules and is placed on the interrupt acknowledge bus vialines 22a, 22c, 22d, etc. The interrupt acknowledge bus 22 is connectedby input bus 22x to master processor module 10a which, in turn, isinterconnected by bus 22xa to resource module 12a and to the othermodules in the daisy chain fashion.

Data bus 26 and address and control bus 28 complete the essential buses,and each of them has bus connections to the modules as follows:connection cables 26a and 28a to processor module 10a; cables 26b and28b to resource module 12a; cables 26c and 28c to processor module 10b;connection cables 26d and 28d to processor module 10c; connection cables26n and 28n to processor module 12n. The multi-master processing busarchitecture shown in FIG. 1 supports a very powerful operating systemthat is extremely small in size and relatively simple in overallcomplexity. The multi-master processor bus signals require differingnumbers of lines in the global bus. The following numbers of lines aretypically required for the specified signals: 23 for Address; 16 forData; 3 for Time Slice Vector; 1 for Device Busy, 1 for Read/Write, 1for Upper Byte Data Strobe; 1 for Lower Byte Data Strobe; 1 for Reset; 1for Global Interrupt Request; 1 Global Interrupt Daisy-Chain In; 1 forGlobal Interrupt Daisy-Chain Out; 1 for Master 16 MHZ Clock; 1 for DataReady; 1 for Interrupt Vector Request; 1 of Global interruptAcknowledge; 1 for Global Interrupt Acknowledge Daisy-Chain In; and 1for Global Interrupt Acknowledge Daisy-Chain Out making a total of 56lines.

Each master processor module 10a, 10b, 10c, 10n is self-sufficient as acomputer system. Preferably, but not necessarily, each master processingmodule is identical to every other module. An encoder means (Not shown)is employed in connection with the counter 16, clock 18, and buffer 20system to assign a given master processor module its time slice, andeach master processor module is given an individual time slice.

Upon system initialization, each master processor module initializes itsown system components. The system components may consist of universalasynchronous receiver transmitters (UARTs), parallel input/outputdevices (PIOs), etc. At this stage, each master processor module thenreads its time slice encoder to determine where in the global memory(predefined points) each successive master processor module can passinformation and commands to the other master processor modules. Eachmaster processor module then clears its own command block and globalmemory and sets a flag that signals other master processor modules thatit is present and functioning properly.

The master processor module, which was assigned a zero time slice byarbitrary choice is designated the master master processor module. Themaster master processor module assumes the duties of the systemsupervisor and is responsible for initializing the global resourcemodules in the system. It also assigns other master processor modules tovarious tasks as needed. Each master processor module as it completesits assigned tasks enters an idle loop and checks its command block andglobal memory for new tasks to perform. The command block is a segmentof memory set up by the master master processor module to allowcommunications among various master processor modules and containscommands, pointers to program and data structures, and status wordsneeded to perform a task.

The various master processor modules are connected in a so-called "daisychain" to other master processor modules. The master master processormodule, if it is the earliest master processor module in the interruptrequest daisy chain 24x, 24xa, 24xb, 24xc, 24xd, . . . 24xn, can be usedto handle all global interrupt requests by always enabling interrupts toitself and inhibiting the interrupt request signals from progagatingthrough the daisy chain to the other master processor modules. Themaster master processor module then performs the required systemfunctions prior to assigning a master processing processor module toprocess the interrupt generated task.

The master master processor module is a supervisor only by default andat any time and for any reason may transfer its system responsibilitiesto any other master processor module. For example, it may detect aninternal hardware fault and trigger the change.

Each master processor module may communicate with other master processormodules through a "back door" (a communication link external to themulti-master processor bus) to allow the system to recover fromcatastrophic faults. For example, it is possible the master masterprocessor module may encounter a severe fault. This ability allows theremaining master processor modules to choose a new master masterprocessor module and ignore the failed master master processor module.If the processor is unable to interrupt the attempted comunications withthe continuously busy resource module after a predetermined time period,the processor will become locked up in the sense that the processor willbe unable to disengage from attempted communications with the busyresource module and consequently will be unable to perform any otherfunctions. The processor will wait indefinitely to communicate with thebusy resource module even though such communications may never beeffected due to a fault in the system. Perhaps a master processor modulewould access a global resource module that was always busy and thiscondition could lock up the master processing module without time-outcapability. Each master processor module should also have internaltime-out capability to enable the master processor module to disengageitself from a global bus transaction in the event of a serious busfault. A processor having a time-out capability can disengage fromperforming a particular function if the function is not performed withina selected time period. Consequently, the time-out capability is asafeguard which prevents a processor from waiting for an indefinite timeperiod to perform a function which may not be possible to effect due toa fault in the system. In other words, the time-out capability helps toprevent the lock up of a processor.

It will be understood that there are other ways of operating the systemof the present invention and the above description is intended to be byway of example of what can be done.

FIG. 2 is an example of an interface between a multi-master processorbus and a processor module for example, a master processor moduleemploying a Motorola 68,000 microprocessor.

Referring now to FIG. 2, the structure shown is a multi-master processorbus/master interface example. As seen in FIG. 2, a processor data bus 34is connected to the global bus 40 through a series of buffers 30a, 30b,and latches 32a and 32b used to collect data from the global bus 40through a global data path 38 by way of input bus 36. The buffers areconventional buffers used to connect to or isolate an individualprocessor and the global bus. The latches are registers used to latchdata from the global bus during those times which are the individualprocessor's time slice. Internal cables connect the processor throughthe cable 34 to the buffers and latches and cable 36 through global datainterchange connects the buffers and latches to the multi-masterprocessor or global bus 40. The interface circuitry, as illustrated, forthe microprocessor, such as the Motorola 68,000 microprocessor, isdesigned to permit the microprocessor to directly execute data from aresource module, for example, as instructions without any need to firstinterpret the data.

In addition to the data interchange to the system described, there is aseries of buffers 42a, 42b, 42c between a common address bus 44 to theprocessor and an output cable 46 to the global address system. Globaladdress contact is made through cable 48 to the multi-master processorbus 40 or global bus. Through this system the global resource isaddressed and selected. Also involved is a global control which may haveto do with other procedural processing factors which are handled throughbuffer 50 through a global control cable 52 to the multi-masterprocessor bus.

The Global Interrupt request daisy chain input and output is representedby lines 58 and 56, respectfully. If this Master Processor module is notto support interrupts, these lines would be connected, thus passing theGlobal Interrupt Request to the next module. If this module is tosupport the Global Interrupts, FIG. 4 describes the appropriatecircuitry.

Line 60 connects the 16 megahertz clock from the global bus to theinterface logic as needed. Line 62 connects the global bus to acomparator 64 which compares the three bits count signal from the lineslice vector bus (GTSV2, GTSV1, GTSV0) with the module's unique timenumber that is encoded by the dip switch 72. The buffer 66 allows theprocessor within the master processor module to read the value encodedby dip switch 72. If the module's number matches the count signal on theglobal bus, the output signal 78 becomes low-active. If this masterprocessor module wants to access the global bus for example, to accessdata (DS) or to respond to a global interrupt (IACK Global Req.), theprocessor causes line 82 to become low active. Thus, the OR gate 80becomes the equivalent to a low level AND gate whose output (when low)indicates that this master processor module wants to access the globalbus and that the count signal matches its own module number. The outputof OR gate 80 is latched by the D-type flip flop 86. The presence ofoutputs at the Q and Q terminals of flip-flop 86 indicates that thismaster processor module has requested and been granted a Valid GlobalRequest (VGR or VGR).

If the master processor module is attempting to write data out onto theglobal bus and into a resource module, the master processor modulecauses the Read/Write line into OR gate 88 to become low active. Thus,if the master processor module has been granted a Valid Global Requestand the request is to write data, the output bus enables signal BEN fromOR gate 88 to become low active. The BEN signal enables the buffers 30aand 30b to pass the data from the module's internal data bus 34 to theglobal data bus 38. The VGR signal from the flip-flop 86 enables theaddress buffers 42a, 42b, 42c and the control buffer 50 to pass theaddress and control signals from the master processor modules addressbus 44 and control bus 45 to the global address control bus. If theResource Module that is addressed by this master processor module isable to accept the data on the global data bus, it will not assert theGBUSY line 92. The "not busy" signal along line 92 is presented to the Dinput terminal of D-type flip-flop 96 and is clocked into flip-flop 96by the VGR signal from flip-flop 86. The Q output of flip-flop 96 isgated through AND gate 98 in the presence of a write not read signal W/Rfrom the processor and passes to the NOR gate 100 to generate a lowactive data transfer acknowledge signal DTACK on line 106. The DTACKsignal is used to notify the processor within this module that thetransaction over the global bus has been completed.

If the master processor module has been granted a valid global requestand is attempting to read data from a resource module on the global databus, and the data from the resource module is ready as indicated by thepresence of a global ready signal GRDY on line 94, a positive goingsignal is generated on the output of the AND gate 90 at the end of thecurrent time slice. The output signal from AND gate 90 is used to clockthe data from the global data bus into the latches 32a and 32b.

The global ready signal (GRDY) on line 94 is also clocked into D-typeflip-flop 102. The output of flip-flop 102 is applied to one input ofAND gate 104. The read not write signal R/W from the processor isapplied to the other input of AND gate 104 to produce an output signal.The output signal from AND gate 104 is fed into NOR gate 100 to generatethe DTACK signal used to indicate to the processor that the read fromthe global resource module has been successfully completed.

The system of FIG. 2A is associated with the system of FIG. 2 andrepresents a logic circuit used by a processor to steer the globalinterrupt request to itself or pass it down the line of processors inconnection with the activity of the global bus. The circuit isrelatively simple consisting of a flip-flop 180 that is controlled bythe processor to steer the global interrupt request GIRQ IN signal.

Depending upon whether the Q or Q output terminals of flip-flop 180 islow active, the respective OR-gate 182 or 184 will pass the Globalinterrupt request daisy chain input signal (GIRQ IN) to the Globalinterrupt request daisy chain output (GIRQ OUT) or to the Interruptrequest line (IRQ) of the modules' processor.

FIG. 3 is an example of the interface logic needed to build a globalresource module. In this example, the module is a memory module withoutthe ability to request global interrupts. It should be noted in thisregard that each module responds to an 8 bit address field. The mostsignificant 8 bits of the address is the module address. The logicinvolves a delay line which is used to match the bandwidth of theincoming request with the bandwidth of the memory devices.

As in FIG. 2, access in FIG. 3 to the global bus 40 is through a globaldata line 38 or through a global address and control line 48/52. Globaldata is provided through buffers 112a and 112b or through registers 114aand 114b. Data is fed through an internal data bus line 34 from the RAMarray 120. RAM array 120 is addressed through the internal address line44. Read and write instructions are given through an internal R/W line51, which is also connected to registers 114a and 114b. The addresspresented by the master processor is fed through the global bus to theglobal address and control lines 48/52 to the registers 116a, 116b, and116c which store the address presented by a master processor, whicheverone is selected. Key data indicating the module number of a masterprocessor module making a read or write request is fed from register116a to the terminals B0, B1, B2 of comparator 122 which compares themodule's number to the current count signal and provides an outputsignal (vector OK) when the comparison is positive. At the same time,the read, not write, signal R/W is inverted by inverter 124 to a write,not read signal W/R which is applied to one terminal of an OR gate 126.The OR gate 126 serves to pass the W/R or the vector OK signal fromcomparator 122 depending upon whether a read or a write has beenrequested by the master processor module making the request.

Global address information is also fed from the global bus line 48 tothe comparator 118 which provides an output whenever the global addressmatches the fixed or hard wired module address. The low active outputfrom the comparator 118 is inverted by inverter 132 and is fed to oneinput of a three input AND gate 134. The output of AND gate 134 is fedto the clock terminal of another D type flip-flop 136 and to the clockinputs of registers 116a, 116b, 116c, 114a and 114b as a strobe (STRB).The AND gate 134 clocks flip-flop 136 when a masterclock signal (MCLK),a module select (output from 132) and a not busy signal (BUSY) coincide.A not busy signal (BUSY) is generated at the Q output of the flip-flop136 when it is actuated by the AND gate 134, and a fixed high actrivesignal V_(x) is present at its D terminal. At the same time busy signalBUSY is generated at the Q terminal of flip-flop 136. The BUSY signal isapplied to the second input of AND gate 128.

A delay line 138 receives the BUSY signal from flip-flop 136 and delaysthe signal for a fixed period before applying it to the clock input offlip-flop 140, the Q input of flip-flop 140 being applied to the thirdinput terminal of AND gate 128. When all three signals are present onthe inputs of AND gate 128, it generates an output signal (DONE) whichis applied to the D input terminal of flip-flop 130. A clear signal fromthe Q output of flip-flop 130 is then applied to clear flip-flops 136and 140 after when the operation is complete. A RESET signal is requiredduring system power up and is applied to flip-flop 130.

The Q output of flip-flop 130 provides an operation complete signalwhich is applied to one input of each of NAND gates 144 and 146. TheNAND gates 144 and 146 generate output signals Global data ready (GDRDY)and Buffer enable (BUFFN) respectively. The BUFFN enables buffers 112aand 112b to put the data onto the global data bus.

FIG. 4 is an example of an interrupt request interface. This interfacemay exist in a global resource module or in a master processor module.When a module requests an interrupt, it must have the interrupt vectorready on its internal data bus 34. Once the interrupt vector isrequested, the interrupt vector is presented through the buffers 112aand 112b through the output cables to the global data line 38 and to themaster processor bus 40. Low active global vector request GIVRO signalis inverted through inverter 148 and applied to one terminal of NANDgate 150 to produce a BEN (used to enable the buffers) and to one inputof NAND gate 152 which produces a low active global device ready signalGDRDY at its output. Each of these NAND gates has a low active inputsignal indicating interrupt acknowledge IACK. The master clock providesan input to clock terminal of D type flip-flop 154 and an IRQ signal isinput at terminal D. The presence of an interrupt request will producean output at each of the Q and Q terminals of D type flip-flop 154 eachbeing applied to one terminal of OR gates 156 and 160, respectively. Asignal (low active) from OR gate 156 will clear the interrupt requestflip-flop 158. Flip-flop 158 receives an edge signal from a devicewithin the module at the clock terminal and a fixed voltage level V_(x)at the D terminal to provide an interrupt request output IRQ at the Qterminal. OR gate 156 will also transmit an IACK signal to NAND gates150 and 152. OR gate 160 also transmits a global acknowledge out signalGIACK OUT to the global bus. When an interrupt request IRQ is generatedat flip-flop 158, that signal is applied through an inverting amplifier162 to provide a low active global interrupt request signal GIRQ to theglobal bus.

FIG. 5 represents a back-plane diagram showing some of the detail of theinterconnection of the multi-master processor bus, or the "global bus"so-called, which has been shown generally in other drawings as member40. The back plane provides plug-in terminal connections for circuitcards and typically a 12 card back plane assembly will fit in a standard19 inch equipment rack. The back plane allows 2 inches of mechanicalmounting overhead. The schematic drawing of FIG. 5 representsconnections for the chip side of the boards connectors. Only connectionsfor the front side of the system or approximately a sixth of the threecircuit boards, for each processor, is represented. The other terminalarrays are similar to those shown, and will be understood to havesimilar arrangements but with different connections. The pull-upresistors are used only for some of the control signals which aregenerated by open-collector gates or for generating default andnon-active command signals in the advent some system boards are removed.The lines between the terminal connections represent hard wiring orcable connections.

The blocks shown 170, 172, and 174 represents the count signal generatoror system controller. Reset in the system is controlled through a resetswitch which applies or removes a signal between a voltage dividerconsisting of a resistor 166 connected to a 5 volt voltage supply andcapacitor 168 connected to ground which signal is applied to aninverting amplifier 164 to generate a signal representative of absenceof global reset GRESET. Normally GRESET is generated out of theamplifier, however, and when the reset switch is applied, that signal isalso generated. In the absence of a reset signal, the count signalgenerator, consisting of the blocks 170, 172, and 174, is operative. Theback plane of the multi-master processor bus or global processor bus 40consist of the three groups of circuits on each side of the board. Thecircuits are represented by connections between terminal points on thedrawing of FIG. 5 and represent one-third of the circuits on theintegrated circuit side of the board. Using this "daisy chain" effect,in some cases the boards in one column, or row, are interconnected withthose in the next row so as to give a sequential transfer effect. Boardconnectors are located in columns or rows, indicated by 176a, 176b,176c, 176d, 176e, through 176n. Inputs to various boards include fixedand variable voltage sources with the resistors 178 to apply apredetermined potential to the input of the first panel which istransferred directly or in succession by the activity along the variouscards.

THEORY OF OPERATION

The present multi-master processor bus system is based on the MC 68,000micro-processor that has a typical bus cycle time of 500 nsec. Thesystem timing controller divides the 500 nsec period into eight 62.5nsec periods, one for each processor module. The time slice vector isgenerated by dividing a 16 MHZ clock with a three bit counter.Therefore, the counter will produce a three bit value which ranges from0₈ to 7₈. Each state of the counter has a period of 62.5 nsec. Thiscycle is repeated every 500 nsec.

Each master processor module will have a 3 bit dip switch that iscontinuously compared to the time slice vector or count signal. When amatch occurs, the given processor module is allowed access onto thesystem if it desires. This 3 bit encoder can be read by the processorand is used to allow the embedded software within the module to know ifit is a master master processor module or just a master processormodule. The master master processor module would assume systemresponsibilities such as initialization until it decided to give up itsresponsibilities to another master processor module.

It is assumed that the other master processor module will initializetheir own subsystems and then quietly wait for instructions from themaster master processor module.

A master processor module that wants to write data into a globalresource module or GRM will wait until its time slice occurs; at whichtime, the master processor module will put Address and Data onto theBus. The GRM's will compare the Address to their own and if the selectedGRM is not busy, the GRM will latch the address and data from the busand begin to process the request. If the GRM is already busy, theprocessor must wait until its next time slice before it can reissue itsrequest.

If a process module wants to read data from a GRM, it puts the addressonto the bus. If the GRM is not busy, the GRM will latch the Address andthe current time slice vector. THE GRM will then process the request.When the GRM has valid data ready, it will wait for the current timeslice vector to be equal the stored value. At that time, the GRM willput the data onto the bus and assert the Data Ready line. The masterprocessor module then latches the data and proceeds with its work. Ifthe GRM has been busy during the initial request, the master processormodule will wait until it is granted access to the Bus. The interfacecircuity, as illustrated, for the microprocessor, such as the MC 68,000microprocessor, is designed to prevent the word length of acommunication between a microprocessor and a global resource module frominhibiting access by any other processor to the same resource module.Since information is processed on a word by word basis as single wordmessages, rather than a multiple word message length basis, a singleprocessor cannot monopolize a particular resource module or even anotherprocessor module to the exclusion of the other processors.

There is no direct memory access or DMA on this Bus. A DMA device wouldbe considered as a master processor and would have its own time slice.

All global interrupts will be "or-tied" together as a common InterruptRequest line. This signal is then daisy-chained through all of theprocessor modules. Each processor may either accept or reject therequest. If it accepts the request, the signal is not propagated throughthe chain; otherwise, the request continues through the chain.

Upon accepting the request, the processor will generate an InterruptAcknowledge that is "or-tied" with the IACK signals from the otherprocessors. This combined signal is then daisy-chained through theinterrupt requestors. The earliest requestor in the chain that hasrequested an interrupt will accept the IACK and the IACK is inhibitedfrom proceeding throught he daisy-chain.

During the following Bus Cycle, the accepting processor will generate aVector Request signal during its time slice. The requesting module willthen present a 16 bit vector onto the Bus and assert the data readysignal. The processor will then latch the vector from the bus.

When a requesting module makes an Interrupt Request, the module willconsider itself busy and will not accept any other request until itsinterrupt is accepted and completed.

FIGS. 6, 7, and 8 are intended to illustrate global system operationalsequences.

FIG. 6 illustrates a write sequence for master processor module number 5which embodies the following steps:

1. Master processor module MPM number 5 internally generates a globalrequest to write data onto a particular GRM. (START);

2. MPM number 5 waits until its time slice occurs;

3. MPM number 5 asserts Address, Data and Control onto the global bus;

4. MPM number 5 encounters a busy signal produced by the addressed GRM;

5. MPM number 5 must wait until its next time slice to write data intothe addressed GRM assuming the addressed GRM is no longer busy.

FIG. 7 illustrates a read sequence for MPM number 2 as follows:

1. MPM number 2 internally generates a global request to read data froma particular GRM (START);

2. MPM waits until its time slice occurs;

3. Assert Address and Control onto global bus;

4. If a Busy signal is asserted, go to line #2;

5. MPM number 2 waits until its next time slice to occur;

6. If the Data Ready signal is asserted, MPM number 2 captures Data fromthe Global bus;

FIG. 8 represents a global interrupt sequence as follows:

1. A system module (master or resource) generates an interrupt requestsignal (START);

2. MPM number 0 responds with an interrupt acknowledge signals (IACK);

3. MPM number 0 then waits until its next time slice occurs. It themasserts the Interrupt vector request signal (IVRQ) and negates the DataStroble (DS) signal;

4. The requesting module puts its interrupt Vector onto the data bus andasserts the Data Ready signal;

5. MPM number 0 latches the interrupt vector from the global data busand negates the Interrupt Acknowledge and vector request signals;

6. (END).

The systems shown in the schematic drawings are intended to berepresentative only. It will be clear to those skilled in the art thatmany variations on those shown may be employed. All such variations areintended to be within the scope and spirit of the present invention.

I claim:
 1. A synchronous data processing system comprising:N processormodules, each processor module including a processor and interfacecircuitry connected with the processor; at least one resource moduleavailable for access by the processor modules; a signal globalmicroprocessor bus system commonly shared by the resource module andeach of the processor modules, the resource module and the interfacecircuitry of each of the processor modules being connected in parallelto the bus system to enable communication among the processor modulesand between the processor modules and the resource module; and systemtiming means connected with the bus system for dividing a predeterminedbus cycle time period into N equal time slices, each processor modulebeing granted access to the global bus for a single time slice duringeach bus cycle time period; the interface circuitry of each processormodule being configured to permit each processor to execute datareceived from a resource module directly as an instruction and beingconfigured to enable each processor module to communicate information insignle word messages during the processor module's respective time sliceso that the length of communication among any two of the processormodules and between any processor module and the resource module doesnot inhibit access by any other processor module to the resource moduleand to either of said two processor modules.
 2. The data processingsystem as recited in claim 1 wherein the processor modules are eachassigned a module number running sequentially from 0 to N-1, and thetime slices are each assigned a number running sequentially from 0 toN-1, each processor module being granted access to the global bus duringthe numbered time slice which corresponds to its module number.
 3. Thedata processing system as recited in claim 2 wherein:the system timingmeans includes a counter for generating consecutive repeating countsignals from 0 to N-1, the counter outputting the count signals onto theglobal bus system; and decoder circuitry within the interface circuitryof each processor module for receiving the count signals and forgranting access to the global bus system when a count signal correspondsto the module number of the particular processor.
 4. The data processingsystem as recited in claim 2 wherein the predetermined bus cycle timeperiod is 500 nanoseconds.
 5. The data processing system as recited inclaims 1 or 4 wherein the global bus system comprises a time slice andclock bus, a data bus and address bus, each of said buses including aplurality of lines.
 6. The data processing system as recited in claim 2wherein the processor modules are all of the same structure and whereinthe module numbers are assigned in a completely arbitrary manner.
 7. Thedata processing system as recited in claim 1 wherein each processormodule is fully self-sufficient and capable of asynchronous operationitself without regard to the global bus.
 8. A synchronous dataprocessing system comprising:N processor modules, each processor moduleincluding a processor and interface circuitry connected with theprocessor; a single global microprocessor bus system commonly shared byeach of the processor modules, the interface circuitry of each of theprocessor modules being connected in parallel to the bus system toenable communication among the processor modules; system timing meansconnected with the bus system for dividing a predetermined bus cycletime period into N equal time slices, each processor module beinggranted to access to the global bus for a single time slice during eachbus cycle time period; the interface circuitry of each processor modulebeing configured to enable each processor module to communicateinformation in single word messages during the processor module'srespective time slice so that the length of communication between anytwo processor modules does not inhibit access by any other processormodule to either of said two processor modules.